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Partcl Pre-Seed YC P25
Faster semiconductor chip design
Partcl uses AI and GPUs to optimize chip design and speed up timing analysis workflows.
Location
San Francisco, CA
Stage
Pre-Seed
Website
partcl.com
LinkedIn
View profile
Artificial IntelligenceGenerative AISemiconductor
Founders
W
William Salcedo ’23
LinkedIn
Looking For
Customer Intros
VP/Director at semiconductor companies responsible for RTL design or physical design. RTL designers/verification engineers
Hiring
Founding Engineer (Systems + ML)
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